Open Architecture Hierarchical Placement for Fpga Datapath Designs

The study of circuit placement in VLSI physical design has been conducted for several decades. As circuit complexity increases, it is non-trivial to place all cells of the circuit within a reasonable time. Many researchers have presented new placement algorithms and tools to address placement issues such as minimization of wire length, routability, and run-time. Our approach is different in that it focuses not on a specific placement algorithm, but on open architecture that provides a general placement API permitting FPGA users to create their own placement algorithms. The placement API is based on the hierarchical grouping of cells and provides common classes and methods for placement. By placing structured datapath circuits in a hierarchical manner, run-time can be significantly decreased while improving placement quality. The circuit’s hierarchical netlist is physically realized as nested bounding boxes, and hierarchical placement, so called Hplacement, is recursively applied to the bounding boxes at each level in a top-down manner, with backtracking used to align ports. We describe design and implementation issues, and the use of H-placement in run-time reconfigurable applications. This research is part of the JHDLBits project combining JBits and JHDL.